(1) Field of the Invention
The present invention relates to a compiler for converting a source program described in a high-level language such as C/C++language into a machine language program, and particularly to a compiler that is capable of outputting a machine language program which can be executed with lower power consumption.
(2) Description of the Related Art
Mobile information processing apparatuses such as mobile phones and personal digital assistants (PDA), which have become widespread in recent years, require reduction of power consumption. Therefore, there is an increasing demand to develop a compiler that is capable of exploiting effectively high functions of a processor used in an information processing apparatus and generating machine-level instructions that can be executed by the processor with low power consumption.
As a conventional compiler, an instruction sequence optimization apparatus for reducing power consumption of a processor by changing execution order of instructions has been disclosed in Japanese Laid-Open Patent Application No. 8-101777.
This instruction sequence optimization apparatus permutes the instructions so as to reduce hamming distances between bit patterns of the instructions without changing dependency between the instructions. Accordingly, it can realize optimization of an instruction sequence, which brings about reduction of power consumption of a processor.
However, the conventional instruction sequence optimization apparatus does not suppose a processor that can execute parallel processing. Therefore, there is a problem that the optimum instruction sequence cannot be obtained even if the conventional optimization processing is applied to the processor with parallel processing capability.